Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies.
In another “rabbit hole moment,” I lost myself in a bout of reminiscence on the Internet Archive’s Wayback Machine. A prehistoric SemiSerious blog post from 2009 attempted to provide updates from ISSCC 2009. TechInsights engineers Aaron Murray, James Bull, and Mohammad Ahmad provided the boots on the ground reports to HQ. I believe these three fine gentlemen all continue their yeoman’s work at the Ottawa company.
Orlando, FL, October 15, 2020 – Micross Components, Inc. (“Micross”), the world’s largest supplier of value-added bare die and a leading global mission-critical microelectronic components and services provider for high-reliability markets and SemiQ, Inc., a developer and manufacturer of silicon carbide (SiC) power devices, modules and epitaxial wafers have signed a new agreement establishing Micross as an authorized worldwide supplier of SemiQ SiC products offered in Die Form.
SANTA CLARA, Calif.–(BUSINESS WIRE)– What’s New: The U.S. Department of Defense has awarded Intel Federal LLC the second phase of its State-of-the-Art Heterogeneous Integration Prototype (SHIP) program. The SHIP program enables the U.S. government to access Intel’s state-of-the-art semiconductor packaging capabilities in Arizona and Oregon and take advantage of capabilities created by Intel’s tens of billions of dollars of annual R&D and manufacturing investment.
The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs.Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce power, and improve time to market. Each package type is different, with various tradeoffs. As before, the idea behind advanced packaging is to assemble complex dies in a package, creating a system-level design. But advanced packaging faces some technical and cost challenges.
Mention an electronic circuit and you are likely to picture a printed circuit board (PCB): a rigid rectangle in a characteristic green color with copper lines and a bewildering array of components soldered onto it. But does adding electronic functionality means using a PCB and thus requires shoehorning a rigid rectangle into the product?
Orlando, FL, January 15, 2020 – Micross is pleased to announce that its Advanced Interconnect Technology operation (Micross AIT) located in Research Triangle Park, North Carolina has been accredited by the Defense Microelectronics Activity (DMEA) as a Microelectronics Trusted Source for Post CMOS Processing Services (Category 1A) effective December 13, 2019.
Researchers at Pohang University of Science and Technology (POSTECH) exploit resistive switching property in halide perovskite materials to develop the basis for a new type of fast, low-power, nonvolatile memory. Halide perovskite materials exhibit a resistive switching property, which means that with the application of a voltage, the substance’s resistance will change.
Feb 28, 2020 – Micro-Precision Technologies, Inc., (MPT) a Salem, NH Defense company was acquired by Aerospace Semiconductor, Inc. (ASI) of Lawrence, MA. Going forward the company will operate under the Micro-Precision Technology, Inc. name in Salem, NH with a DBA registered for the Aerospace Semiconductor, Inc. name in Lawrence, MA.
The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge.This doesn’t mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme to one or more of those leading-edge chips or chiplets. The challenge will be verifying and debugging all of these devices in the context of how they will be used, and then testing them repeatedly in the lab, in manufacturing, during and after packaging, and for as long as they are used in the field.