Gearing Up For Hybrid Bonding

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chip-lets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and enables smaller, thinner packages with faster memory/processor speeds — and all of this while consuming less power.

Source: Gearing Up For Hybrid Bonding