Next Challenge: Known Good Systems
The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge.This doesn’t mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme to one or more of those leading-edge chips or chiplets. The challenge will be verifying and debugging all of these devices in the context of how they will be used, and then testing them repeatedly in the lab, in manufacturing, during and after packaging, and for as long as they are used in the field.
