Multi-Die Design Pushes Complexity To The Max
Multi-die/multi-chiplet design has thrown a wrench into the ability to manage design complexity, driving up costs per transistor, straining market windows, and sending the entire chip industry scrambling for new tools and methodologies. For multiple decades, the entire semiconductor design ecosystem — from EDA and IP providers to foundries and equipment makers — has evolved with the assumption that more functionalities can be added into chips and packages, while improving the power, performance, and area/cost equation. But as the ability to pack all of this functionality into a single die or package becomes more difficult, the complexity of developing these devices has skyrocketed.
